svenkata has asked for the wisdom of the Perl Monks concerning the following question:
Hi all,
I have a simple piece of code to create Verilog templates using perl where I have to execute something like this:
print "module(
...
...
$display("The time is %d",$time)\n";
If I try to escape the $ and " I still get a compile error and when I escape even the paranthesis ( then it works
Can someone tell me why this is happening when paranthesis is not one of the characters that need to be escaped in a perl string enclosed in "
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