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Re^4: verilog perl usage (Verilog::Netlist)

by mahurshi (Initiate)
on Mar 15, 2009 at 06:14 UTC ( #750703=note: print w/ replies, xml ) Need Help??

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  1. or download this
    cat top.v
    module top (a, b, c, d);
    ...
    buffer i_buffer (.in_b(b), .out_d(d));
    
    endmodule
    
  2. or download this
    %Error: top.v:10: Cannot find buffer
    %Error: top.v:9: Cannot find inverter
    ...
        PinName=out_d NetName=d
        PinName=in_a NetName=a
        PinName=out_c NetName=c
    

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