note Amblikai <p>I like the first one you wrote, i hadn't come across that operator. Seems exactly the same as a conditional statement in Verilog. So it's still pretty readable to me! </p> <p>Regarding your footnote, supposing i didn't need 0 for false, how would i do it? And how else can you represent false? </p> <p> Thanks very much for your very helpful reply. </p> 1010917 1010918