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Re^3: verilog perl usage (Verilog::Netlist)

by toolic (Chancellor)
on Mar 15, 2009 at 01:31 UTC ( #750691=note: print w/ replies, xml ) Need Help??


in reply to Re^2: verilog perl usage
in thread verilog perl usage

would love to switch to this package and get rid of my buggy parsing subroutines.
You are a wise monk, indeed. I have also come to realize that parsing Verilog is not a trivial matter. Every time I get the urge to do so, I take a step back and ask myself these questions:
  1. Can any of the tools for which my $company pays millions of dollars per annum already do what I need?
  2. Are there any free tools available out on the 'net which can do what I need?

If the answer to the above is "no", then I turn to Perl.

would love to switch to using Verilog::Perl if it makes things simpler
Since I have not used these tools, I can not comment on their capabilities or limitations. However, according to the documentation, they seem quite useful. I think it is well worth a try.
point me to a website with such examples
I have done some searching, but I have not found any examples. I encourage you to give it a try, and report back here if you discover anything. CPAN modules usually have an "examples" directory in the install area. Have you looked there?
Could you also show an example of how to identify the ports of the module, what blocks are instantiated in it, what ports those blocks have, and what they're connected to
Sure. This is my first program using Verilog::Netlist (see also Re^3: verilog-perl vhier usage). I merely adapted the EXAMPLE given in the POD on CPAN.
> cat top.v module top; buff b0 (); endmodule module buff (buf_in, buf_out); input buf_in; inout out; wire a; inv i0 (.in(buf_in), .out(a )); inv i1 (.in(a ), .out(buf_out)); endmodule module inv (in, out); input in; output out; assign out = ~in; endmodule > > cat example.pl #!/usr/bin/env perl use strict; use warnings; use Verilog::Netlist; # prepare netlist my $nl = new Verilog::Netlist(); $nl->read_file(filename => './top.v'); # read in any sub modules $nl->link(); $nl->lint(); $nl->exit_if_error(); print "Module names in netlist:\n"; for my $mod ( $nl->modules() ) { print $mod->name(), "\n"; } print "\n"; for my $mod ( $nl->top_modules_sorted() ) { show_hier($mod, '', '', ''); } sub show_hier { # Recursively descend through module hierarchy, # printing each module name and full hierarchical # specifier, all module port names, and all # instance port connections. my $mod = shift; my $indent = shift; my $hier = shift; my $cellname = shift; if ($cellname) { $hier .= ".$cellname"; } else { $hier = $mod->name(); } print "${indent}ModuleName=", $mod->name(), " HierInstName=$hier\n +"; $indent .= ' '; for my $sig ($mod->ports_sorted()) { print $indent, 'PortDir=', sigdir($sig->direction()), ' PortNam +e=', $sig->name(), "\n"; } for my $cell ($mod->cells_sorted()) { for my $pin ($cell->pins_sorted()) { print $indent, ' PinName=', $pin->name(), ' NetName=', $pin +->netname(), "\n"; } show_hier($cell->submod(), $indent, $hier, $cell->name()) if $c +ell->submod(); } } sub sigdir { # Change "in" to "input" # Change "out" to "output" my $dir = shift; return ($dir eq 'inout') ? $dir : $dir . 'put'; } > > ./example.pl Module names in netlist: buff inv top ModuleName=top HierInstName=top ModuleName=buff HierInstName=top.b0 PortDir=input PortName=buf_in PortDir=inout PortName=out PinName=in NetName=buf_in PinName=out NetName=a ModuleName=inv HierInstName=top.b0.i0 PortDir=input PortName=in PortDir=output PortName=out PinName=in NetName=a PinName=out NetName=buf_out ModuleName=inv HierInstName=top.b0.i1 PortDir=input PortName=in PortDir=output PortName=out >
My Verilog example code is extremely simple. I can not guarantee it will work for whatever code you have. But, give it a try.

May I ask what you plan to do with the parsed output?


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Re^4: verilog perl usage (Verilog::Netlist)
by mahurshi (Initiate) on Mar 15, 2009 at 06:14 UTC
    Thanks a lot again for your second example. This is really along the lines of what I am expecting out of the parser. What I want to do (eventually) with the parsing really depends on how much I am able to do with it :-). At the very minimum, I would like to identify the instantiations, port names, widths, connections, etc to do various kinds of post processing. Coming back to the piece of code you posted: I was able to get it to work by commenting out the exit_if_error() part. I have to admit first that I still need to spend some time to learn what each of these function calls really mean. Here is the example code I tried to test it with:
    cat top.v module top (a, b, c, d); input a; input b; output c; output d; inverter i_inverter (.in_a(a), .out_c(c)); buffer i_buffer (.in_b(b), .out_d(d)); endmodule
    Granted, this is not much, but this is enough for a starter like me :-) What I didn't give the script were the module definitions of "inverter" and "buffer" modules. I still expected it to at least write out the instantiation names and their port connections. I agree with the error messages below from the scripts output, but I don't understand why doesn't show the instantiation names. Why doesn't it associate the pin names (in_*, out_*) to the instantiation names? Does it absolutely require module references for that?
    %Error: top.v:10: Cannot find buffer %Error: top.v:9: Cannot find inverter %Error: top.v:10: Module reference not found: buffer %Error: top.v:9: Module reference not found: inverter Exiting due to errors Module names in netlist: top ModuleName=top HierInstName=top PortDir=input PortName=a PortDir=input PortName=b PortDir=output PortName=c PortDir=output PortName=d PinName=in_b NetName=b PinName=out_d NetName=d PinName=in_a NetName=a PinName=out_c NetName=c
    Thanks again for your help
      Does it absolutely require module references for that?
      I do not know. You now have as much working experience as I do with Verilog-Perl. It seems reasonable that Verilog::Netlist would require you to provide the sub-module definitions (just as all simulators do). OTOH, I can understand why you might want them to be treated like black boxes. All I can offer is this generic advice:
      1. Read (and re-read) the POD.
      2. Try experimenting with more methods and options.
      3. Start studying the Perl source code. Perhaps the functionality you desire is buried in there. If not, maybe it becomes obvious to you how to alter the source code to do what you want.
      4. Try browsing (or asking a question on) the CPAN Verilog Discussion forum: http://www.cpanforum.com/dist/Verilog-Perl.
      5. As a last resort, try contacting the author. There must be some reason CPAN authors provide an email address :)
        It turns out to be very simple. :-) It looks as though you weren't printing the instance (cell) names. It did what I wanted when i changed the below line
        print $indent, ' PinName=', $pin->name(), ' NetName=', $pin->netname()
        to
        print $indent, ' CellName=', $cell->name(), ' PinName=', $pin->name(), + ' NetName=', $pin->netname()
        Thanks again

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