The characters [] are special in regexes, and you need to escape them with \Q...\E aka quotemeta. If I replace ${port_name} with \Q$port_name\E, I get the output "$port_name = sdm_yout_i[1] cell name = dout_sar". If you want the "cell name" to be "sdm_yout_i", you need to further restrict your regex and replace the .*? just before $port_name with something like \W*.
But this still all feels a bit like a hack. You've been advised to use real Verilog parsers like Verilog::VCD and Verilog-Perl in four separate threads now (out of five total). Perhaps it's about time you looked into getting those installed?
