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verilog perl usage

by perlvoyager (Initiate)
on Feb 25, 2009 at 19:25 UTC ( #746354=perlquestion: print w/ replies, xml ) Need Help??
perlvoyager has asked for the wisdom of the Perl Monks concerning the following question:

Greetings perl monks I am new to Verilog -perl and would really appreciate if anybody could tell me how to use the CPAN verilog -perl scripts like vhier and packages like verilog ::parser.I have downloaded and installed verilog perl. Any sample code using maybe vhier to start with will be really helpful

Comment on verilog perl usage
Re: verilog perl usage
by toolic (Chancellor) on Feb 25, 2009 at 21:56 UTC
    I do have these tools installed, but I have not used them much. This may be way too basic for what you're asking, but here is what I know...

    To get help on vhier:

    $ vhier --help

    To show all the Verilog modules in a file:

    $ cat top.v module top; dff i0 (); endmodule module dff; endmodule $ $ vhier top.v --modules dff top

    Adapting the EXAMPLE code from Verilog::Parser:

    use warnings; use strict; package MyParser; use Verilog::Parser; our @ISA = qw(Verilog::Parser); # parse, parse_file, etc are inherited from Verilog::Parser sub new { my $class = shift; #print "Class $class\n"; my $self = $class->SUPER::new(); bless $self, $class; return $self; } sub symbol { my $self = shift; my $token = shift; $self->{symbols}{$token}++; } sub report { my $self = shift; foreach my $sym (sort keys %{$self->{symbols}}) { printf "Symbol %-30s occurs %4d times\n", $sym, $self->{symbol +s}{$sym}; } } package main; my $text = <<"EOF"; module m; reg ina, inb; endmodule EOF my $parser = MyParser->new(); $parser->parse($text); $parser->eof(); $parser->report(); __END__ Output: Symbol ina occurs 1 times Symbol inb occurs 1 times Symbol m occurs 1 times

    See also: http://www.veripool.org/wiki/verilog-perl

    What are you trying to do?

      Thanks toolic,appreciate your help.the information was very useful. I am trying to do the following a)open the files in a given directory/subdirectories-only files with extension .v/.vh/.svn/.sv/.svi. At present concentrating on only .v and .vh b)search for verilog module definition c)for each module that is defined more than once the list of all files(full path /relative path) in which the module is defined should be printed. d)must be able to exclude // from parsing i figured out i could do much of the stuff using o the vhier,but i am unsure of how to use the verilog arguments like 1.+incdir+dir =item -Idir Add the directory to the list of directories that should be searched for include directories or libraries. 2.and also the vhier -f file:Read the specified file, and act as if all text inside it was specified as command line parameters. Should a filehandle be passed or just the filename? I know this sounds really silly asking such basic questions but I am good at writing perl code rather than using packages Would appreciate if you could throw some light on this. Thanks
        It looks like vhier can do all the things you want to do. The script accepts filenames, just like any standard unix command. Just give it a try.
        $ vhier -f file.txt --modules --input-files
      Excellent example. Could you also show an example of how to identify the ports of the module, what blocks are instantiated in it, what ports those blocks have, and what they're connected to.. If you could show me one or two examples, or perhaps, point me to a website with such examples, that would be great. I am currently parsing files manually but would love to switch to using Verilog::Perl if it makes things simpler. My goal is to be able to access ports of the module, identify all the instantiations of other blocks in a module, find out what ports are present in those instantations for each block, and what wires they are connected to. I am currently stuck with parsing the files manually and building hash tables to get this info but would love to switch to this package and get rid of my buggy parsing subroutines.
        would love to switch to this package and get rid of my buggy parsing subroutines.
        You are a wise monk, indeed. I have also come to realize that parsing Verilog is not a trivial matter. Every time I get the urge to do so, I take a step back and ask myself these questions:
        1. Can any of the tools for which my $company pays millions of dollars per annum already do what I need?
        2. Are there any free tools available out on the 'net which can do what I need?

        If the answer to the above is "no", then I turn to Perl.

        would love to switch to using Verilog::Perl if it makes things simpler
        Since I have not used these tools, I can not comment on their capabilities or limitations. However, according to the documentation, they seem quite useful. I think it is well worth a try.
        point me to a website with such examples
        I have done some searching, but I have not found any examples. I encourage you to give it a try, and report back here if you discover anything. CPAN modules usually have an "examples" directory in the install area. Have you looked there?
        Could you also show an example of how to identify the ports of the module, what blocks are instantiated in it, what ports those blocks have, and what they're connected to
        Sure. This is my first program using Verilog::Netlist (see also Re^3: verilog-perl vhier usage). I merely adapted the EXAMPLE given in the POD on CPAN. My Verilog example code is extremely simple. I can not guarantee it will work for whatever code you have. But, give it a try.

        May I ask what you plan to do with the parsed output?

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