use warnings;
use strict;

package MyParser;
use Verilog::Parser;
our @ISA = qw(Verilog::Parser);

# parse, parse_file, etc are inherited from Verilog::Parser
sub new {
     my $class = shift;
     #print "Class $class\n";
     my $self = $class->SUPER::new();
     bless $self, $class;
     return $self;
}

sub symbol {
     my $self = shift;
     my $token = shift;

     $self->{symbols}{$token}++;
}

sub report {
     my $self = shift;

     foreach my $sym (sort keys %{$self->{symbols}}) {
        printf "Symbol %-30s occurs %4d times\n", $sym, $self->{symbols}{$sym};
     }
}

package main;

my $text = <<"EOF";
module m;

    reg ina, inb;

endmodule
EOF

my $parser = MyParser->new();
$parser->parse($text); $parser->eof();
$parser->report();


__END__

Output: 

Symbol ina                            occurs    1 times
Symbol inb                            occurs    1 times
Symbol m                              occurs    1 times