Could you also show an example of how to identify the ports of the module, what blocks are instantiated in it, what ports those blocks have, and what they're connected to..
If you could show me one or two examples, or perhaps, point me to a website with such examples, that would be great.
I am currently parsing files manually but would love to switch to using Verilog::Perl if it makes things simpler. My goal is to be able to access ports of the module, identify all the instantiations of other blocks in a module, find out what ports are present in those instantations for each block, and what wires they are connected to. I am currently stuck with parsing the files manually and building hash tables to get this info but would love to switch to this package and get rid of my buggy parsing subroutines.
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in thread verilog perl usage