> cat top.v
module top;
   buff b0 ();
endmodule

module buff (buf_in, buf_out);
   input buf_in;
   inout out;
   wire  a;
   inv i0 (.in(buf_in), .out(a      ));
   inv i1 (.in(a     ), .out(buf_out));
endmodule

module inv (in, out);
   input  in;
   output out;
   assign out = ~in;
endmodule
>
> cat example.pl
#!/usr/bin/env perl

use strict;
use warnings;
use Verilog::Netlist;

# prepare netlist
my $nl = new Verilog::Netlist();
$nl->read_file(filename => './top.v');

# read in any sub modules
$nl->link();
$nl->lint();
$nl->exit_if_error();

print "Module names in netlist:\n";
for my $mod ( $nl->modules() ) {
   print $mod->name(), "\n";
}
print "\n";

for my $mod ( $nl->top_modules_sorted() ) {
   show_hier($mod, '', '', '');
}

sub show_hier {
   # Recursively descend through module hierarchy,
   # printing each module name and full hierarchical
   # specifier, all module port names, and all
   # instance port connections.
   my $mod      = shift;
   my $indent   = shift;
   my $hier     = shift;
   my $cellname = shift;
   if ($cellname) {
       $hier .= ".$cellname";
   }
   else {
       $hier = $mod->name();
   }
   print "${indent}ModuleName=", $mod->name(), "  HierInstName=$hier\n";
   $indent .= '   ';

   for my $sig ($mod->ports_sorted()) {
       print $indent, 'PortDir=', sigdir($sig->direction()), ' PortName=', $sig->name(), "\n";
   }

   for my $cell ($mod->cells_sorted()) {
       for my $pin ($cell->pins_sorted()) {
           print $indent, ' PinName=', $pin->name(), ' NetName=', $pin->netname(), "\n";
       }

       show_hier($cell->submod(), $indent, $hier, $cell->name()) if $cell->submod();
   }
}

sub sigdir {
   # Change "in"  to "input"
   # Change "out" to "output"
   my $dir = shift;
   return ($dir eq 'inout') ? $dir : $dir . 'put';
}

>
> ./example.pl
Module names in netlist:
buff
inv
top

ModuleName=top  HierInstName=top
  ModuleName=buff  HierInstName=top.b0
     PortDir=input PortName=buf_in
     PortDir=inout PortName=out
      PinName=in NetName=buf_in
      PinName=out NetName=a
     ModuleName=inv  HierInstName=top.b0.i0
        PortDir=input PortName=in
        PortDir=output PortName=out
      PinName=in NetName=a
      PinName=out NetName=buf_out
     ModuleName=inv  HierInstName=top.b0.i1
        PortDir=input PortName=in
        PortDir=output PortName=out
>