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Re^4: verilog perl usage (Verilog::Netlist)

by mahurshi (Initiate)
on Mar 15, 2009 at 06:14 UTC ( #750703=note: print w/ replies, xml ) Need Help??


in reply to Re^3: verilog perl usage (Verilog::Netlist)
in thread verilog perl usage

Thanks a lot again for your second example. This is really along the lines of what I am expecting out of the parser. What I want to do (eventually) with the parsing really depends on how much I am able to do with it :-). At the very minimum, I would like to identify the instantiations, port names, widths, connections, etc to do various kinds of post processing. Coming back to the piece of code you posted: I was able to get it to work by commenting out the exit_if_error() part. I have to admit first that I still need to spend some time to learn what each of these function calls really mean. Here is the example code I tried to test it with:

cat top.v module top (a, b, c, d); input a; input b; output c; output d; inverter i_inverter (.in_a(a), .out_c(c)); buffer i_buffer (.in_b(b), .out_d(d)); endmodule
Granted, this is not much, but this is enough for a starter like me :-) What I didn't give the script were the module definitions of "inverter" and "buffer" modules. I still expected it to at least write out the instantiation names and their port connections. I agree with the error messages below from the scripts output, but I don't understand why doesn't show the instantiation names. Why doesn't it associate the pin names (in_*, out_*) to the instantiation names? Does it absolutely require module references for that?
%Error: top.v:10: Cannot find buffer %Error: top.v:9: Cannot find inverter %Error: top.v:10: Module reference not found: buffer %Error: top.v:9: Module reference not found: inverter Exiting due to errors Module names in netlist: top ModuleName=top HierInstName=top PortDir=input PortName=a PortDir=input PortName=b PortDir=output PortName=c PortDir=output PortName=d PinName=in_b NetName=b PinName=out_d NetName=d PinName=in_a NetName=a PinName=out_c NetName=c
Thanks again for your help


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Re^5: verilog perl usage (Verilog::Netlist)
by toolic (Chancellor) on Mar 15, 2009 at 14:13 UTC
    Does it absolutely require module references for that?
    I do not know. You now have as much working experience as I do with Verilog-Perl. It seems reasonable that Verilog::Netlist would require you to provide the sub-module definitions (just as all simulators do). OTOH, I can understand why you might want them to be treated like black boxes. All I can offer is this generic advice:
    1. Read (and re-read) the POD.
    2. Try experimenting with more methods and options.
    3. Start studying the Perl source code. Perhaps the functionality you desire is buried in there. If not, maybe it becomes obvious to you how to alter the source code to do what you want.
    4. Try browsing (or asking a question on) the CPAN Verilog Discussion forum: http://www.cpanforum.com/dist/Verilog-Perl.
    5. As a last resort, try contacting the author. There must be some reason CPAN authors provide an email address :)
      It turns out to be very simple. :-) It looks as though you weren't printing the instance (cell) names. It did what I wanted when i changed the below line
      print $indent, ' PinName=', $pin->name(), ' NetName=', $pin->netname()
      to
      print $indent, ' CellName=', $cell->name(), ' PinName=', $pin->name(), + ' NetName=', $pin->netname()
      Thanks again

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