in reply to
Re^3: verilog perl usage (Verilog::Netlist)
in thread verilog perl usage
Thanks a lot again for your second example. This is really along the lines of what I am expecting out of the parser.
What I want to do (eventually) with the parsing really depends on how much I am able to do with it :-). At the very minimum, I would like to identify the instantiations, port names, widths, connections, etc to do various kinds of post processing.
Coming back to the piece of code you posted: I was able to get it to work by commenting out the exit_if_error() part. I have to admit first that I still need to spend some time to learn what each of these function calls really mean.
Here is the example code I tried to test it with:
module top (a, b, c, d);
inverter i_inverter (.in_a(a), .out_c(c));
buffer i_buffer (.in_b(b), .out_d(d));
Granted, this is not much, but this is enough for a starter like me :-)
What I didn't give the script were the module definitions of "inverter" and "buffer" modules. I still expected it to at least write out the instantiation names and their port connections.
I agree with the error messages below from the scripts output, but I don't understand why doesn't show the instantiation names. Why doesn't it associate the pin names (in_*, out_*) to the instantiation names? Does it absolutely require module references for that?
%Error: top.v:10: Cannot find buffer
%Error: top.v:9: Cannot find inverter
%Error: top.v:10: Module reference not found: buffer
%Error: top.v:9: Module reference not found: inverter
Exiting due to errors
Module names in netlist:
Thanks again for your help