Re: Verilog parse:vhier to get input/output ports (Verilog::Netlist)

Comment on Re: Verilog parse:vhier to get input/output ports (Verilog::Netlist)

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Re^2: Verilog parse:vhier to get input/output ports (Verilog::Netlist) by perlUser345 (Acolyte) on May 24, 2016 at 16:50 UTC
I did. The problem is I can't get the port sizes for inputs/outputs. Like if it's `input [7:0] test`, how do I get the `[7:0]`?	[reply] [d/l] [select]
Re^2: Verilog parse:vhier to get input/output ports (Verilog::Netlist) by Anonymous Monk on Jun 10, 2016 at 07:51 UTC
cant we do without using verilog::netlist ? can i get a glimse of how we can do without using any packages	[reply]


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