my $match = "(?<=module )$ARGV[2].*?([\\(;])";
print "$match";

my $filename = $ARGV[0];

open (INFILE, "<", $filename)  or  die "Failed to read file $filename : $! \n";

$string =  <INFILE>;
close INFILE;

$string =~ s/$match/$ARGV[1]$1/sg;
print "$1";


##</code><code>##

script.pl f5 NEW OLD
(?<=module )OLD.*?([\(;])
#> cat f5
//Verilog HDL for "tt", "hh" "functional"
// if i write the word module here the script goofs up
`timescale 1ps/10fs


module NEW(Y, A, B );
    output Y;
    input A;
    input B;

endmodule