Re: want to ignore pattern under{} in split command

As toolic has remarked, it looks like you want to write a Verilog parser for yourself rather than use an established module (employment insurance?). If so, the recent saga of herman4016 may be helpful. Also, typing 'Verilog' into Super Search may help.

Give a man a fish: <%-(-(-(-<

Comment on Re: want to ignore pattern under{} in split command Download Code

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Re^2: want to ignore pattern under{} in split command by jag194u (Initiate) on May 28, 2015 at 03:51 UTC
Thanks toolic ...it worked for me.	[reply]
Re^3: want to ignore pattern under{} in split command by AnomalousMonk (Archbishop) on May 28, 2015 at 04:01 UTC
You're very welcome — it was good for me, too. But I am not toolic. Give a man a fish: `<%-(-(-(-<`	[reply] [d/l]
Re^4: want to ignore pattern under{} in split command by jag194u (Initiate) on May 28, 2015 at 16:53 UTC
HI Toolic, similar to {*} can be treated as {} in the earlier solution by you if i have `write_x($psprintf("mod.ins[%d].ins[%d].val",1,2),{24'h0,4'h2,variable1 +,variable2},status,"s +tring");` [download] any inputs how to make the split command to read the below into single word..i have tried few ways but in vain. `$psprintf("mod.ins[%d].ins[%d].val",1,2)` [download]	[reply] [d/l] [select]
Re^5: want to ignore pattern under{} in split command by AnomalousMonk (Archbishop) on May 28, 2015 at 19:50 UTC


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