my.pl f7 NEW OLD Now parsing f7 Matching: (?<=module )OLD.*?([\(;]) READING LINE //Verilog HDL for "tt", "hh" "functional" // if i write the word module OLD(Y, A, B ); here the script goofs up `timescale 1ps/10fs module OLD(Y, A, B ); output Y; input A; input B; endmodule INSIDE IF