use warnings; use strict; while () { chomp; s/(.+?)OLD(?=\()/$1NEW/; print $_, $/; } __DATA__ //Verilog HDL for "tt", "hh" "functional" // if i write the word module here the script goofs up `timescale 1ps/10fs module OLD(Y, A, B ); output Y; input A; input B; endmodule #### while () { chomp; s/(.+?)OLD/$1NEW/ unless m{//}; print $_, $/; } __DATA__ //Verilog HDL for "tt", "hh" "functional" // if i write the word module here the script goofs up `timescale 1ps/10fs module OLD(Y, A, B ); output Y; input A; input B; endmodule #### //Verilog HDL for "tt", "hh" "functional" // if i write the word module here the script goofs up `timescale 1ps/10fs module NEW(Y, A, B ); output Y; input A; input B; endmodule