in reply to Bug in script, regex help req extreme urgent
Hi sid.verycool
Using the data set you provided,
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you could use lookahead assertion like so:
use warnings; use strict; while (<DATA>) { chomp; s/(.+?)OLD(?=\()/$1NEW/; print $_, $/; } __DATA__ //Verilog HDL for "tt", "hh" "functional" // if i write the word module here the script goofs up `timescale 1ps/10fs module OLD(Y, A, B ); output Y; input A; input B; endmodule
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you can also use the wisdom of CountZero
while (<DATA>) { chomp; s/(.+?)OLD/$1NEW/ unless m{//}; print $_, $/; } __DATA__ //Verilog HDL for "tt", "hh" "functional" // if i write the word module here the script goofs up `timescale 1ps/10fs module OLD(Y, A, B ); output Y; input A; input B; endmodule
//Verilog HDL for "tt", "hh" "functional" // if i write the word module here the script goofs up `timescale 1ps/10fs module NEW(Y, A, B ); output Y; input A; input B; endmodule
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