note
2teez
<p>
Hi [sid.verycool]<br>
Using the data set you provided,
<ul>
<li>
you could use lookahead assertion like so:
<c>
use warnings;
use strict;
while (<DATA>) {
chomp;
s/(.+?)OLD(?=\()/$1NEW/;
print $_, $/;
}
__DATA__
//Verilog HDL for "tt", "hh" "functional"
// if i write the word module here the script goofs up
`timescale 1ps/10fs
module OLD(Y, A, B );
output Y;
input A;
input B;
endmodule
</c></li>
<li>
you can also use the wisdom of [CountZero]
<c>
while (<DATA>) {
chomp;
s/(.+?)OLD/$1NEW/ unless m{//};
print $_, $/;
}
__DATA__
//Verilog HDL for "tt", "hh" "functional"
// if i write the word module here the script goofs up
`timescale 1ps/10fs
module OLD(Y, A, B );
output Y;
input A;
input B;
endmodule
</c>
</li></ul>
<i>Output:</i>
<c>
//Verilog HDL for "tt", "hh" "functional"
// if i write the word module here the script goofs up
`timescale 1ps/10fs
module NEW(Y, A, B );
output Y;
input A;
input B;
endmodule
</c>
</p>
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<div class="pmsig"><div class="pmsig-918402">
If you tell me, I'll forget.<br>
If you show me, I'll remember.<br>
if you involve me, I'll understand.<br>
--- Author [unknown to me]
</div></div>
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