Re^2: Bug in script, regex help req extreme urgent

[sid.verycool]

If i do

my $match = "(?<=module ).*?$ARGV[2].*?([\\(;])";

Then the output is

//Verilog HDL for "tt", "hh" "functional"
// if i write the word module module NEW(Y, A, B );
    output Y;
    input A;
    input B;

endmodule

this does not solve the issue :(