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Re: Bug in script, regex help req extreme urgent

by 2teez (Priest)
on Mar 09, 2013 at 13:47 UTC ( #1022574=note: print w/ replies, xml ) Need Help??


in reply to Bug in script, regex help req extreme urgent

Hi sid.verycool
Using the data set you provided,

  • you could use lookahead assertion like so:
    use warnings; use strict; while (<DATA>) { chomp; s/(.+?)OLD(?=\()/$1NEW/; print $_, $/; } __DATA__ //Verilog HDL for "tt", "hh" "functional" // if i write the word module here the script goofs up `timescale 1ps/10fs module OLD(Y, A, B ); output Y; input A; input B; endmodule
  • you can also use the wisdom of CountZero
    while (<DATA>) { chomp; s/(.+?)OLD/$1NEW/ unless m{//}; print $_, $/; } __DATA__ //Verilog HDL for "tt", "hh" "functional" // if i write the word module here the script goofs up `timescale 1ps/10fs module OLD(Y, A, B ); output Y; input A; input B; endmodule
Output:
//Verilog HDL for "tt", "hh" "functional" // if i write the word module here the script goofs up `timescale 1ps/10fs module NEW(Y, A, B ); output Y; input A; input B; endmodule

If you tell me, I'll forget.
If you show me, I'll remember.
if you involve me, I'll understand.
--- Author unknown to me


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