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Re: Verilog parse:vhier to get input/output ports (Verilog::Netlist)by toolic (Bishop) |
on May 23, 2016 at 17:38 UTC ( [id://1163891]=note: print w/replies, xml ) | Need Help?? |
vhier does not print out ports, but Verilog::Netlist does. Here is an example:
Re^3: verilog perl usage (Verilog::Netlist)
In Section
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