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This is where you can search for all the writeups contributed by any user. Just enter the user name and select the order for the search.

These nodes all have stuff by herman4016 (showing 1-19 out of ~19^?):

Node ID	Writeup	Created
1119733	Re^2: Regular Expressions with varialbe with "[]"	2015-03-12 02:41
1119731	Re^2: Regular Expressions with varialbe with "[]" (Verilog)	2015-03-12 02:27
1119501	Regular Expressions with varialbe with "[]"	2015-03-10 13:54
1115488	Re^4: how to extract multiple pattern into array	2015-02-04 07:25
1115330	Re^2: how to extract multiple pattern into array	2015-02-03 02:07
1115262	how to extract multiple pattern into array	2015-02-02 06:13
1114499	Re^4: how to split file with some pattern (Verilog)	2015-01-26 10:10
1114487	Re^2: how to split file with some pattern (Verilog)	2015-01-26 02:06
1114432	Re^2: how to split file with some pattern (Verilog)	2015-01-25 13:24
1114261	Re^2: how to split file with some pattern	2015-01-23 10:16
1114239	how to split file with some pattern	2015-01-23 07:32
1097927	Re^6: extract text from multi-line context (Verilog::VCD)	2014-08-19 02:55
1097778	Re^4: extract text from multi-line context (Verilog::VCD)	2014-08-18 02:54
1097657	Re^4: extract text from multi-line context	2014-08-16 09:08
1097654	Re^2: extract text from multi-line context (Verilog::VCD)	2014-08-16 08:32
1097534	Re^2: extract text from multi-line context	2014-08-15 10:12
1097529	extract text from multi-line context	2014-08-15 08:53
1079500	Re^2: how to write multi-line regex	2014-03-24 09:08
1079475	how to write multi-line regex	2014-03-24 03:40

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