in reply to
Coverting Case statements of verilog to equations.
You can use Verilog-Perl to parse the Verilog source code (as I mentioned in a previous post), but I think you need to do the rest yourself.
Priority 1, Priority 2, Priority 3
Priority 1, Priority 0, Priority -1
Urgent, important, favour
Data loss, bug, enhancement
Out of scope, out of budget, out of line
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Impossible, inconceivable, implemented
Results (70 votes),