in reply to
Coverting Case statements of verilog to equations.
You can use Verilog-Perl to parse the Verilog source code (as I mentioned in a previous post), but I think you need to do the rest yourself.
Non-existent; I don't have TV
Non-existent; my TV doesn't have/need a remote
Under my control; I watch alone
Under the control of whoever shouts loudest
Under the control of whoever gets it first
One of many, and the TV has a mind of its own
Results (574 votes),