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Re: Coverting Case statements of verilog to equations.

by toolic (Bishop)
on Apr 02, 2012 at 17:07 UTC ( #963064=note: print w/replies, xml ) Need Help??


in reply to Coverting Case statements of verilog to equations.

You can use Verilog-Perl to parse the Verilog source code (as I mentioned in a previous post), but I think you need to do the rest yourself.
  • Comment on Re: Coverting Case statements of verilog to equations.

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