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| Pathologically Eclectic Rubbish Lister | |
| PerlMonks |
Re: Coverting Case statements of verilog to equations.by toolic (Chancellor) |
| on Apr 02, 2012 at 17:07 UTC ( #963064=note: print w/ replies, xml ) | Need Help?? |
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You can use Verilog-Perl to parse the Verilog source code (as I mentioned in a previous post), but I think you need to do the rest yourself.
In Section
Seekers of Perl Wisdom
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