in reply to
Coverting Case statements of verilog to equations.
You can use Verilog-Perl to parse the Verilog source code (as I mentioned in a previous post), but I think you need to do the rest yourself.
I make decisions, and my brain carries them out
My brain makes the decisions, and I observe them (if I'm lucky)
I make some decisions, and my brain makes others
My spouse makes decisions and I and my brain carry them out
I wrote a program to relieve me and my brain from the burden of decision-making
The black-helicopter people project the decisions into my brain and then I do as ordered
Results (361 votes),