in reply to Re^2: verilog perl usage
in thread verilog perl usage

would love to switch to this package and get rid of my buggy parsing subroutines.
You are a wise monk, indeed. I have also come to realize that parsing Verilog is not a trivial matter. Every time I get the urge to do so, I take a step back and ask myself these questions:
  1. Can any of the tools for which my $company pays millions of dollars per annum already do what I need?
  2. Are there any free tools available out on the 'net which can do what I need?

If the answer to the above is "no", then I turn to Perl.

would love to switch to using Verilog::Perl if it makes things simpler
Since I have not used these tools, I can not comment on their capabilities or limitations. However, according to the documentation, they seem quite useful. I think it is well worth a try.
point me to a website with such examples
I have done some searching, but I have not found any examples. I encourage you to give it a try, and report back here if you discover anything. CPAN modules usually have an "examples" directory in the install area. Have you looked there?
Could you also show an example of how to identify the ports of the module, what blocks are instantiated in it, what ports those blocks have, and what they're connected to
Sure. This is my first program using Verilog::Netlist (see also Re^3: verilog-perl vhier usage). I merely adapted the EXAMPLE given in the POD on CPAN.
> cat top.v module top; buff b0 (); endmodule module buff (buf_in, buf_out); input buf_in; inout out; wire a; inv i0 (.in(buf_in), .out(a )); inv i1 (.in(a ), .out(buf_out)); endmodule module inv (in, out); input in; output out; assign out = ~in; endmodule > > cat #!/usr/bin/env perl use strict; use warnings; use Verilog::Netlist; # prepare netlist my $nl = new Verilog::Netlist(); $nl->read_file(filename => './top.v'); # read in any sub modules $nl->link(); $nl->lint(); $nl->exit_if_error(); print "Module names in netlist:\n"; for my $mod ( $nl->modules() ) { print $mod->name(), "\n"; } print "\n"; for my $mod ( $nl->top_modules_sorted() ) { show_hier($mod, '', '', ''); } sub show_hier { # Recursively descend through module hierarchy, # printing each module name and full hierarchical # specifier, all module port names, and all # instance port connections. my $mod = shift; my $indent = shift; my $hier = shift; my $cellname = shift; if ($cellname) { $hier .= ".$cellname"; } else { $hier = $mod->name(); } print "${indent}ModuleName=", $mod->name(), " HierInstName=$hier\n +"; $indent .= ' '; for my $sig ($mod->ports_sorted()) { print $indent, 'PortDir=', sigdir($sig->direction()), ' PortNam +e=', $sig->name(), "\n"; } for my $cell ($mod->cells_sorted()) { for my $pin ($cell->pins_sorted()) { print $indent, ' PinName=', $pin->name(), ' NetName=', $pin +->netname(), "\n"; } show_hier($cell->submod(), $indent, $hier, $cell->name()) if $c +ell->submod(); } } sub sigdir { # Change "in" to "input" # Change "out" to "output" my $dir = shift; return ($dir eq 'inout') ? $dir : $dir . 'put'; } > > ./ Module names in netlist: buff inv top ModuleName=top HierInstName=top ModuleName=buff HierInstName=top.b0 PortDir=input PortName=buf_in PortDir=inout PortName=out PinName=in NetName=buf_in PinName=out NetName=a ModuleName=inv HierInstName=top.b0.i0 PortDir=input PortName=in PortDir=output PortName=out PinName=in NetName=a PinName=out NetName=buf_out ModuleName=inv HierInstName=top.b0.i1 PortDir=input PortName=in PortDir=output PortName=out >
My Verilog example code is extremely simple. I can not guarantee it will work for whatever code you have. But, give it a try.

May I ask what you plan to do with the parsed output?