Hi all,
Good day to all...
I have two files as follows.
File1 is as follows....
architecture DEF_ARCH of fulladder_postsyn is
component INBUF
port( PAD : in std_logic := 'U';
Y : out std_logic
);
end component;
component OUTBUF
port( D : in std_logic := 'U';
PAD : out std_logic
);
end component;
component VCC
port( Y : out std_logic
);
end component;
component XOR3
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component GND
port( Y : out std_logic
);
end component;
component MAJ3
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
signal \GND\, \VCC\, N_5, a_c, b_c, c_c, sum_c, GND_0, VCC_0
: std_logic;
File2 is as follows..
component XOR2
port (A : in std_logic := 'U';
B : in std_logic := 'U';
Y : out std_logic);
end component;
I want to insert file2 in file1 either after architecture line or before signal line... i.e. i want to insert this component in this component declaration part....Give me some idea to do this monks....