// Generated for: spectre
// Generated on: Jul 26 15:10:24 2016
// Design library name: custom
// Design cell name: TOPLEVEL
// Design view name: schematic
simulator lang=spectre
global 0
//--------------------------------//
// Library name: custom
// Cell name: inv
// View name: schematic
subckt inv IN OUT VDD VSS
    M0 (OUT IN VSS VSS) nch l=60n w=200n m=1 nf=1 sd=200n ad=3.5e-14 \
        as=3.5e-14 pd=750n ps=750n nrd=0.5 nrs=0.5 sa=175n sb=175n sca=0 \
        scb=0 scc=0
    M2 (OUT IN VDD VDD) pch l=60n w=200n m=1 nf=1 sd=200n ad=3.5e-14 \
        as=3.5e-14 pd=750n ps=750n nrd=0.5 nrs=0.5 sa=175n sb=175n sca=0 \
        scb=0 scc=0
ends inv
// End of subcircuit definition.

// Library name: custom
// Cell name: BUF_DELAY
// View name: schematic
subckt BUF_DELAY IN OUT VDD VSS
    I1 (net11 OUT VDD VSS) inv
    I0 (IN net11 VDD VSS) inv
ends BUF_DELAY
// End of subcircuit definition.

// Library name: custom
// Cell name: INV_DELAY
// View name: schematic
subckt INV_DELAY IN OUT VDD VSS
    I2 (net08 OUT VDD VSS) inv
    I1 (net11 net08 VDD VSS) inv
    I0 (IN net11 VDD VSS) inv
ends INV_DELAY
// End of subcircuit definition.

// Library name: custom
// Cell name: TOPLEVEL
// View name: schematic
I2 (BUF_IN BUF_OUT VDD VSS) BUF_DELAY
I3 (INV_IN INV_OUT VDD VSS) INV_DELAY
I4 (INV_IN net8) isource type=pwl wave=[ 1u 1 2u 2 ]
V3 (VSS 0) vsource dc=0 type=dc
V2 (INV_IN 0) vsource dc=0 type=dc
V1 (BUF_IN 0) vsource dc=5 type=dc
V0 (VDD 0) vsource dc=5 type=dc
R0 (net8 VSS) rm1w l=10u w=2u mf=1
C0 (net8 0) capacitor c=1p

//----------------- Entering Netlist Footer -------------------//