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Re: Store data into array by looping?

by tybalt89 (Monsignor)
on Apr 10, 2019 at 00:52 UTC ( [id://1232377]=note: print w/replies, xml ) Need Help??


in reply to Store data into array by looping?

Looks like you are taking the same course as Output not correct

Anyway, here's a small simulator I wrote from that input (slightly modified for case) that processes your input and simulates the circuit, providing all inputs and producing a table with all outputs.

It stores gates in a hash keyed by output name where the value is perl code to evaluate the output from the inputs. This allows easy simulation later when all gates are combined to a generated sub call 'async'.

This form of gate storage may or may not be what you are looking for.

#!/usr/bin/perl # https://perlmonks.org/?node_id=1226380 # https://perlmonks.org/?node_id=1232356 use strict; use warnings; my (%gates, @inputs, @wires, @outputs, $depends, %bits, $topologicalor +der); while( <DATA> ) # inpu +t section { print; if( /^nand /gi ) { my ( undef, $out, $ina, $inb) = /\w+/g; $gates{$out} and die "\nDUPLICATE: $out\n"; $gates{$out} = "1 ^ (\$bits{'$ina'} & \$bits{'$inb'})"; $depends .= "$out $ina $inb\n"; } elsif( /^output /gi ) { push @outputs, /\w+/g; } elsif( /^input /gi ) { push @inputs, /\w+/g; } elsif( /^wire /gi ) { push @wires, /\w+/g; } } my @all = (@inputs, @wires, @outputs); #use Data::Dump 'dd'; dd \%gates; %gates or die "no gates found"; $depends =~ s/ $_\b//g for @inputs; # topological orde +r section while( $depends =~ s/^(\w+)\n//m ) { $topologicalorder .= "\$bits{$1} = $gates{$1};\n"; $depends =~ s/ $1\b//g; } length $depends and die "CIRCULAR or UNDEFINED:\n<$depends>"; print $topologicalorder; eval "sub async { $topologicalorder }"; my $fmt = "@{[ map '%' . y///c . 's', @all ]}\n"; # outpu +t section printf $fmt, @all; @bits{@all} = ('u') x @all; for ( glob '{0,1}' x @inputs ) { @bits{@inputs} = map 0 + $_, split //; async(); printf $fmt, @bits{@all}; } __DATA__ module circuit_17 (N1,N2,N3,N6,N7,N22,N23); input N1,N2,N3,N6,N7; output N22,N23; wire N10,N11,N16,N19; nand nand2_1 (N10,N1,N3); nand nand2_2 (N11,N3,N6); nand nand2_3 (N16,N11,N2); nand nand2_4 (N19,N11,N7); nand nand2_5 (N22,N10,N16); nand nand2_6 (N23,N16,N19); endmodule

Seems to work. May have issues if you start using tri-state output logic.

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